1. Field of the Invention
The present invention relates to the field of microprocessor architecture. More specifically, the present invention relates to a mechanism for minimizing main memory references initiated during context switches.
2. Art Background
The evolution of semiconductor technology has enabled microprocessors and microcontrollers today to be more powerful than room-sized computers a few decades ago. As processing chips become faster, the data traffic between a processor and off-chip main memory increases, resulting in a performance bottleneck. One approach to reducing the bottleneck is the use of a small high-speed local memory called a cache integrated on the processing chip itself.
A cache memory is used to store frequently used memory locations. If data required by the processor is in the cache, an off-chip memory reference is avoided since the data can be fetched directly from the on-chip cache. Further reductions in memory traffic are achieved by expanding cache memory designs to provide for caching frequently used instructions to reduce the time required for instruction fetching. Along the lines of data and instruction caches, there is also an efficiency increase obtainable by utilizing an on-chip stack frame cache such as that described by U.S. Pat. No. 4,811,208 issued Mar. 7, 1989 and assigned to the assignee of the present invention. An on-chip stack frame cache is an efficient memory used to store a set of registers during a context switch. A context switch is a call or interrupt that allows new code to execute with a new register set. The old register set is saved in the stack frame cache for retrieval upon returning from the context switch.
When a stack frame cache becomes full, the oldest register set in it has to be stored out to main memory. The time to do this depends greatly on the speed of the off-chip memory. The action of storing a frame of registers from a given context to main memory is referred to as a frame spill. A frame spill will greatly delay the execution of the existing (current) program. This is suboptimal where some context switches, such as critical interrupts, need to be executed with minimal delay. It would be advantageous, and is therefore an object of the present invention, to provide a mechanism for preserving on-chip resources for these critical events to prevent the delay of a frame spill.